Re: Where's the parallelize step?

I still think thats not quite the same thing as originally posed.

While I belive your right that the below example "could be parallized" by a 
conforming processor.
There still is the other set of features which xproc does not have 
reguarding explicitly saying operations are to be done in parallel.  This is 
in the realm of workflow languages and modeling such as BPEL.  To do these 
it takes more then allowing a processor to parallize tasks, but it also 
requires semantics to "JOIN" parallel tasks predictably (wait until one, 
several, or all complete).
For example, I dont belive XProc has any semantics to say "Wait until any 
one of pipelines A,B or C completes then execute D, canceling the 2 which 
did not complete first.

It would definately be nice to have this feature but I could see why the 
authors wouldnt want to go down that path (atleast for V1) ... It adds a lot 
of complexity to both the specs and the implementation.   Also the common 
use cases for this kind of control parallelism I'm not so sure are the 
common use cases for xproc (yet).   Workflow parallisims (say in BPEL) often 
from the need to control tasks which have external triggers, for example it 
may be very critical to say "Wait until an invoice is either paid or 
rejected or until 30 days elapse", when its (imho) not so critical to say 
"Wait until either the xslt or xquery is finished.".

-David


----- Original Message ----- 
From: "Costello, Roger L." <costello@mitre.org>
To: <xproc-dev@w3.org>
Sent: Monday, April 20, 2009 9:00 AM
Subject: RE: Where's the parallelize step?



Hi Henry,

Ah, I see. Very clever.

Okay. I think that works.

Thanks! I'll add this to my tutorial.

/Roger


> -----Original Message-----
> From: Henry S. Thompson [mailto:ht@inf.ed.ac.uk]
> Sent: Monday, April 20, 2009 8:49 AM
> To: Costello, Roger L.
> Cc: 'xproc-dev@w3.org'
> Subject: Re: Where's the parallelize step?
>
> -----BEGIN PGP SIGNED MESSAGE-----
> Hash: SHA1
>
> Costello, Roger L. writes:
>
> > I think there is a difference between:
> >
> >  - an XProc processor recognizing that some
> >    steps can be run in parallel
> >
> >    versus
> >
> >  - a user creating an XML workflow, declaring
> >    that "steps A, B, C can be run in parallel
> >    with steps D, E, F"
> >
> >
> > The former is an XProc processor optimization activity. The latter
> > is a user modeling activity.
> >
> > I think that it is important for a user to be able to explicitly
> > state in an XProc document "These two workflow activities
> > (subpipelines) may be run in parallel." (Whether an XProc processor
> > executes the subpipelines in parallel or serially is an
> > implementation issue.)
>
> Hmm, I'm worried we still have a disconnect.
>
> If I write the following pipeline:
>
>   <p:declare-step name="top">
>    <p:input port="i1" primary="false"/>
>    <p:input port="i2" primary="false"/>
>
>    <p:output port="o1" primary="false">
>     <p:pipe step="sp1b" port="result"/>
>    </p:output>
>
>    <p:output port="o2" primary="false">
>     <p:pipe step="sp2b" port="result"/>
>    </p:output>
>
>    <p:... name="sp1a">
>     <p:input>
>      <p:pipe step="top" port="i1"/>
>     </p:input>
>    </p:...>
>     . . .
>    <p:... name="sp1b">
>     . . .
>    </p:...>
>
>    <p:... name="sp2a">
>     <p:input>
>      <p:pipe step="top" port="i2"/>
>     </p:input>
>    </p:...>
>     . . .
>    <p:... name="sp2b">
>     . . .
>    </p:...>
>
>   </p:declare-step>
>
> do you think there is something that _prevents_ the two sub-pipelines
> - From running in parallel if you _don't_ say they can?  If so, I
> believe that's a misreading of the spec.
>
> It is of course open to you to add
>
>  <p:documentation>Note that the implicit subpipe beginning
> with this step
>          and ending with step sp1b may run in parallel with
>          the implicit subpipe beginning with step
> sp2a.</p:documentation>
>
> to sp1a, but we don't need a language change to make that possible.
>
> How is what you have in mind different from this?
>
> ht
> - -- 
>        Henry S. Thompson, School of Informatics, University
> of Edinburgh
>                          Half-time member of W3C Team
>       10 Crichton Street, Edinburgh EH8 9AB, SCOTLAND -- (44)
> 131 650-4440
>                 Fax: (44) 131 651-1426, e-mail: ht@inf.ed.ac.uk
>                        URL: http://www.ltg.ed.ac.uk/~ht/
> [mail really from me _always_ has this .sig -- mail without
> it is forged spam]
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Received on Monday, 20 April 2009 13:34:52 UTC