- From: <Toman_Vojtech@emc.com>
- Date: Thu, 8 Oct 2009 10:07:06 -0400
- To: <public-xml-processing-model-comments@w3.org>
Another potential risk is that, because not knowing the declarations of V2 steps, a V1 processor may accept statically a V2 pipeline that actually contains static errors and would be rejected by V2 processors. For instance: <p:pipeline> <p:v1-step-that-initiates-vacuum-phase-transition/> <p:v2-step/> </pipeline> Now, suppose the declaration of p:v2-step sais that the step has no primary output port. Then a V2 processor would reject the pipeline (provided the rules for static errors don't change much from V1). A V1 processor, however, might decide to accept the pipeline statically (by making some assumptions about p:v2-step) and run it. Of course, you should get a dynamic error if the processor attempted to evaluate the V2 step, but in this case, the processor would never get that far... But maybe this is OK. After all, it's about forward compatibility and running V2 pipelines with V1 processors will always have its risks. Regards, Vojtech
Received on Thursday, 8 October 2009 14:20:46 UTC