5.3.3 Cell header algorithm

Header information is available from the document source

User agents should use the algorithm to calculate header information provided in the HTML 4.0 specification ([HTML40], section 11.4.3).

[Ed. The following issues were raised by Harvey Bingham.]

  1. TH cells on both the left and right of the table need to be considered.
  2. For TH cells with "rowspan" set: the content of those TH cells must be considered for each of the N-1 rows below the one containing that TH content.
  3. An internal TH in a row surrounded on either side by TDs has no means to specify to which (row or column) that TH overrides what existed to its left or above it.
  4. Finding column header cells assumes they are all above the TD cell to which they apply.
  5. A TH with "colspan" set needs to be included in the list of TH for the M-1 columns to the right of the column in which the TH is found.

[Ed. The following issues were raised by Jon Gunderson]

  1. Multiple rows or columns of header cells

Example:

TH Information is not available from the document source

If an author of a data table does not supply information about which cells in the table are the headers by using either the TH element or using the SCOPE attribute, the user agent should allow the user to make assumptions about which cells in the table are being used for header information. By assuming header cells a table can be made more understandable when using speech or refreshable Braille displays. The user should be oriented to the problem and be able to choose the algorithm used to determine which cells are header cells.

First Column

First row algorithm:

1. Find the right most cell in the current row and include row span cells in the right most search.

2. Find the top most cell of a column and include column span cells in the search

3. A clue to using the first row assumption would be to check the first cell in every row has content and that the number of data elements is the same in each row.

Example: The following table is an example of a table where the first row could be used as header cells. The first data cell would be assumed to a data cell would be the cell in the second row and first column. It could be rendered through a speech synthesizer as "Issue number sign 3".

Open Issues
Issue # Name Description Date Type Resolution First Working Draft Comments and Reference URLs
3 Al Gilman What should UAs do with recognize navigation bars? Mon Apr 19 17:15:04 1999 Checkpoints Not resolved No reference Comments and Key References
34 Jon Gunderson Allow the user to view assumed headers associated with a cell Tue Apr 20 17:17:25 1999 Checkpoints Not resolved No reference Comments
40 Denis Anson What types of navigation commands support visually impaired users navigating a unfamilar document? Wed Apr 28 17:23:36 1999 Issue Not resolved No reference None
First column and first row

First row and first column algorithm:

1. Find the right most cell in the current row and include row span cells in the right most search.

2. Find the top most cell of a column and include column span cells in the search

3. A clue to using the first row and first column assumption would be to check the first cell as an empty cell.

Example: The following table does not indicate which cells are header cells in the markup. The header cells though are clearly the first row and first column. The first data cell would be assumed to a data cell would be the cell in the second row and column. It could be rendered through a speech synthesizer as "hp omni book cpu speed intel 400-, 366-, 333-, or 300 mhz mobile pentium i i processor"

  HP OmniBook
4150 Series
HP OmniBook
900 Series
HP OmniBook
XE2 Series

CPU Speed

Intel 400-, 366-, 333-, or 300-MHz Mobile Pentium II processor

Intel 400-, 366- or 300PE-MHz Mobile Pentium II processor

Intel 366-, 333- or 300PE-MHz Mobile Pentium II or 333- or 300-MHz Mobile Celeron processor

Cahce

512-KB pipeline-burst asynchronous L2 cache (for 300-MHz models) 256-KB on-board 4-way set-associative L2 cache (for 400-, 366- and 333-MHz models) and 32-KB internal L1 cache

256-KB on-board 4-way set-associative L2 cache and 32-KB internal L1 cache

256- or 128-KB embedded pipeline-burst synchronous L2 cache and 32-KB internal L1 cache

Memory

128 or 64 MB of SDRAM standard; expandable to 256 MB

32 MB standard; expandable to 160 MB

64 or 32 MB of SDRAM standard; expandable to 256 MB

Mass
Storage

10.1-billion-byte (9.41-GB) or 6.4-billion-byte (5.96-GB) or 4.8-billion-byte (5.96-GB) removable Enhanced-IDE hard drive; 3.5-inch, 1.44-MB floppy disk drive module; optional 24X-maximum-speed CD-ROM drive, LS-120 SuperDisk, 4X DVD-ROM3 drive, and second 6.4-billion-byte hard disk drive modules

6.4-billion-byte (5.96-GB) or 4.3-billion-byte (4.01-GB) removable Enhanced-IDE hard drive; 3.5-inch, 1.44-MB floppy disk drive module; optional 24X-maximum-speed CD-ROM drive, LS-120 SuperDisk, 4X DVD-ROM drive, and second 10.1-billion-byte (9.41-GB) hard disk drive modules

6.26-billion-byte (5.83-GB) or 4.1-billion-byte (3.82-GB) removable Enhanced-IDE hard drive; built-in, 3.5-inch, 1.44-MB floppy disk drive; built-in 24X-maximum-speed CD-ROM drive

Display

14.1" 102x768 XGA TFT with 16 million colors

12.1" 800x600 SVGA TFT display with 16 million colors

13.3" diagonal 1024x768 XGA TFT display with 65,536 colors or 12.1" diagonal 800x600 SVGA HPA or TFT display with 16 million colors4