Re: Syntax

Alessandro Vernet wrote:
>> 3. Omitting exactly one required p:output on a step and exactly one
>>    required p:input on the following step implies that that output
>>    is connected to that input. (Alternatively, components could nominate
>>    default inputs and outputs and those could be connected together by
>>    default.)
> 
> 
> Not sure about this though. We went back and forth on the issue of
> implicit connections between steps. The counter-argument is that with
> implicit connections one can't know if two steps are connected or not
> connected without knowing the interface the components used in the
> steps. Comparing this to regular programming languages, it is like
> saying that if you see:
> 
>    step1()
>    step2()

I tend to agree with this opinion too. This can even get worse, for 
instance, when defining a step s1 with an implicit input after two 
parallel steps p1 & p2. Should this be disallowed? If not, would s1's 
input be linked into p2's output or p1's output? Either way, it will 
complicate the spec.


Cheers,
Rui